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8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
n 14 MHz Operation at 2.7-3.3 Volts n 1 Mbyte of Linear Address Space n Optional 4 Kbytes of ROM n 1000 Bytes of Register RAM n Register-register Architecture n 32 I/O Port Pins n 16 Prioritized Interrupt Sources n 4 External Interrupt Pins and NMI Pin n 2 Flexible 16-bit Timer/Counters with Quadrature Counting Capability n 3 Pulse-width Modulator (PWM) Outputs with High Drive Capability n Full-duplex Serial Port with Dedicated Baud-rate Generator n Peripheral Transaction Server n Event Processor Array (EPA) with 4 Highspeed Capture/Compare Channels
The 8XL196NP is a member of Intel's 16-bit MCS(R) 96 microcontroller family. The device features 1 Mbyte of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch between multiplexed and demultiplexed operation. When operating at 14 MHz in demultiplexed mode, the 8XL196NP can access a 200 ns memory device with zero wait states. The 8XL196NP is available without ROM (80L196NP) or with 4 Kbytes of ROM (83L196NP).
n Chip-select Unit -- 6 Chip Select Pins -- Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each Chip Select -- Programmable Wait States (0, 1, 2, or 3) for Each Chip Select -- Programmable Bus Width (8- or 16bit) for Each Chip Select -- Programmable Address Range for Each Chip Select n 2.0s 16 x 16 Unsigned Multiplication n 3.4s 32/16 Unsigned Division n 100-pin SQFP or 100-pin QFP Package n Complete System Development Support n High-speed CHMOS Technology
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information contained herein supersedes previously published specifications on these devices from Intel. Order Number: 272824-001 (c) INTEL CORPORATION, 1996 March 1996
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
16 CPU 1000 Byte Register File 4K Bytes ROM (optional)
RALU
Interrupt Controller
24 Bytes CPU SFRs
Microcode Engine
Peripheral Transaction Server 8 16
Memory Controller with Chip Select Queue
Chip Select CS5:0#
Control Signals A19:16/ EPORT3:0
A15:0 Pulse Width Modulator
Timer 1 Timer 2
Event Processor Array
Serial Port
Baud Rate Gen
AD15:0
Port 1
Port 2
Port 3
Port 4
Port 1/ EPA3:0, Timer 1, Timer 2
Port 2/ Hold Control, SIO, EXTINT1:0
Port 3/ Port 4/ EXTINT3:2 PWM2:0
A2351-01
Figure 1. 8XL196NP Block Diagram
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8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
1.0 NOMENCLATURE OVERVIEW
X
Te
XX
ck Pa
8
X
o Pr
X
o Pr
XXXXX
o Pr
XX
De
Table 1. Description of Product Nomenclature Parameter Temperature and Burn-in Options Packaging Options Program-memory Options Process Information Product Family Device Speed Options no mark S SB 0 3 L 196NP no mark 14 MHz Description Commercial operating temperature range (0C to 70C) with Intel standard burn-in. QFP SQFP No ROM ROM Low Voltage CHMOS
mp
vic
gr am
ce
du
Figure 2. 8XL196NP Family Nomenclature
tio ns Op tio in Op nur ing ag dB an re ns
pe eS
atu er
ss Inf or ma yO em or pti on s
ct Fa
-m
mi ly
ed
tio n
A2815-01
3
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
2.0 PINOUT
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
AD1 AD2 AD3 AD4 AD5 AD6 AD7 VCC AD8 VSS AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 / EPORT.0 A17 / EPORT.1 VCC
AD0 NC RESET# NMI EA# A0 A1 VCC VSS A2 A3 A4 A5 A6 A7 VCC VSS NC P3.0 / CS0# P3.1 / CS1# P3.2 / CS2# P3.3 / CS3# VSS P3.4 / CS4# P3.5 / CS5# P3.6 / EXTINT2 NC P3.7 / EXTINT3 P1.0 / EPA0 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
S8XL196NP
View of component as mounted on PC board
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS A18 / EPORT.2 A19 / EPORT.3 WR# / WRL# RD# BHE# / WRH# ALE INST READY RPD ONCE VSS VCC VSS A8 A9 A10 A11 A12 A13 A14 A15 VSS XTAL1 XTAL2 VSS P2.7 / CLKOUT NC P2.6 / HLDA# P2.5 / HOLD#
P1.1 / EPA1 P1.2 / EPA2 P1.3 / EPA3 P1.4 / T1CLK P1.5 / T1DIR VCC P1.6 / T2CLK VSS P1.7 / T2DIR P4.0 / PWM0 P4.1 / PWM1 P4.2 / PWM2 P4.3 VCC VSS P2.0 / TXD P2.1 / RXD P2.2 / EXTINT0 P2.3 / BREQ# P2.4 / EXTINT1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A4318-01
Figure 3. 8XL196NP 100-pin SQFP Package
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8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 2. 8XL196NP 100-pin SQFP Pin Assignment Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Name RESET# NMI EA# A0 A1 VCC VSS A2 A3 A4 A5 A6 A7 VCC VSS NC NC CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 VSS CS4#/P3.4 CS5#/P3.5 EXTINT2/P3.6
Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Name EXTINT3/P3.7 EPA0/P1.0 VCC EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 T1CLK/P1.4 T1DIR/P1.5 VCC T2CLK/P1.6 VSS T2DIR/P1.7 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 P4.3 VCC VSS TXD/P2.0 RXD/P2.1 EXTINT0/P2.2 BREQ#/P2.3 EXTINT1/P2.4 HOLD#/P2.5 HLDA#/P2.6
Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 NC VSS
Name CLKOUT/P2.7
Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Name WR#/WRL# EPORT.3/A19 EPORT.2/A18 VSS VCC EPORT.1/A17 EPORT.0/A16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 VSS AD8 VCC AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
XTAL2 XTAL1 VSS NC A15 A14 A13 A12 A11 A10 A9 A8 VSS VCC VSS ONCE RPD READY INST ALE BHE#/WRH# RD#
To be compatible with future versions of the Nx family, tie the no connection (NC) pins as follows: Pin 57 = VSS, Pin 16 = VCC, Pin 17 = VSS (5 volts on this pin will enable a clock doubler on future devices), and Pin 52 = VCC.
5
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 3. 100-pin SQFP Pin Assignment Arranged by Functional Categories Address & Data Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 6 Pin 4 5 8 9 10 11 12 13 65 64 63 62 61 60 59 58 82 81 78 77 100 99 98 97 96 95 94 93 91 89 88 87 86 Processor Control Name CLKOUT EA# EXTINT0 EXTINT1 EXTINT2 EXTINT3 NMI ONCE RESET# RPD XTAL1 XTAL2 Pin 51 3 46 48 25 26 2 69 1 70 55 54 ALE BHE#/WRH# BREQ# HOLD# HLDA# INST RD# READY WR#/WRL# Bus Control & Status Name Pin 73 74 47 49 50 72 75 71 76 AD13 AD14 AD15 Address & Data (cont) Name Pin 85 84 83 Input/Output Name CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 CS4#/P3.4 CS5#/P3.5 EPA0/P1.0 EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 EPORT.0 EPORT.1 EPORT.2 EPORT.3 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.6 P3.7 P4.3 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 RXD/P2.1 T1CLK/P1.4 T1DIR/P1.5 T2CLK/P1.6 T2DIR/P1.7 TXD/P2.0 Pin 18 19 20 21 23 24 27 29 30 31 82 81 78 77 46 47 48 49 50 51 25 26 41 38 39 40 45 32 33 35 37 44 NC NC NC NC No Connection Name Pin 16 17 52 57 VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Power & Ground Name Pin 6 14 28 34 42 67 80 92 7 15 22 36 43 53 56 66 68 79 90
RESET# NMI EA# A0 A1 VCC VSS A2 A3 A4 A5 A6 A7 VCC VSS NC NC P3.0 / CS0# P3.1 / CS1# P3.2 / CS2# P3.3 / CS3# VSS P3.4 / CS4# P3.5 / CS5# P3.6 / EXTINT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
SB8XL196NP
View of component as mounted on PC board
Figure 4. 8XL196NP 100-pin QFP Package
A4317-01
P3.7 / EXTINT3 P1.0 / EPA0 VCC P1.1 / EPA1 P1.2 / EPA2 P1.3 / EPA3 P1.4 / T1CLK P1.5 / T1DIR VCC P1.6 / T2CLK VSS P1.7 / T2DIR P4.0 / PWM0 P4.1 / PWM1 P4.2 / PWM2 P4.3 VCC VSS P2.0 / TXD P2.1 / RXD P2.2 / EXTINT0 P2.3 / BREQ# P2.4 / EXTINT1 P2.5 / HOLD# P2.6 / HLDA#
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VCC AD8 VSS AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 / EPORT.0 A17 / EPORT.1 VCC VSS A18 / EPORT.2 A19 / EPORT.3 WR# / WRL#
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RD# BHE# / WRH# ALE INST READY RPD ONCE VSS VCC VSS A8 A9 A10 A11 A12 A13 A14 A15 NC VSS XTAL1 XTAL2 VSS NC P2.7 / CLKOUT
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
7
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 4. 8XL196NP 100-pin QFP Pin Assignment Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AD0 No Connection RESET# NMI EA# A0 A1 VCC VSS A2 A3 A4 A5 A6 A7 VCC VSS No Connection CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 VSS CS4#/P3.4 CS5#/P3.5 Name Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name EXTINT2/P3.6 No Connection EXTINT3/P3.7 EPA0/P1.0 VCC EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 T1CLK/P1.4 T1DIR/P1.5 VCC T2CLK/P1.6 VSS T2DIR/P1.7 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 P4.3 VCC VSS TXD/P2.0 RXD/P2.1 EXTINT0/P2.2 BREQ#/P2.3 EXTINT1/P2.4 Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name HOLD#/P2.5 HLDA#/P2.6 No Connection CLKOUT/P2.7 VSS XTAL2 XTAL1 VSS A15 A14 A13 A12 A11 A10 A9 A8 VSS VCC VSS ONCE RPD READY INST ALE BHE#/WRH# Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 RD# WR#/WRL# EPORT.3/A19 EPORT.2/A18 VSS VCC EPORT.1/A17 EPORT.0/A16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 VSS AD8 VCC AD7 AD6 AD5 AD4 AD3 AD2 AD1 Name
8
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 5. 100-pin QFP Pin Assignment Arranged by Functional Categories Address & Data Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 Pin 6 7 10 11 12 13 14 15 66 65 64 63 62 61 60 59 83 82 79 78 1 100 99 98 97 96 95 94 92 90 89 88 87 9 Processor Control Name CLKOUT EA# EXTINT0 EXTINT1 EXTINT2 EXTINT3 NMI ONCE RESET# RPD XTAL1 XTAL2 Pin 54 5 48 50 26 28 4 70 3 71 57 56 ALE BHE#/WRH# BREQ# HOLD# HLDA# INST RD# READY WR#/WRL# Bus Control & Status Name Pin 74 75 49 51 52 73 76 72 77 AD13 AD14 AD15 Address & Data (cont) Name Pin 86 85 84 Input/Output Name CS0#/P3.0 CS1#/P3.1 CS2#/P3.2 CS3#/P3.3 CS4#/P3.4 CS5#/P3.5 EPA0/P1.0 EPA1/P1.1 EPA2/P1.2 EPA3/P1.3 EPORT.0 EPORT.1 EPORT.2 EPORT.3 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.6 P3.7 P4.3 PWM0/P4.0 PWM1/P4.1 PWM2/P4.2 RXD/P2.1 T1CLK/P1.4 T1DIR/P1.5 T2CLK/P1.6 T2DIR/P1.7 TXD/P2.0 Pin 19 20 21 22 24 25 29 31 32 33 83 82 79 78 48 49 50 51 52 54 26 28 43 40 41 42 47 34 35 37 39 46 NC NC NC NC No Connection Name Pin 2 18 27 53 VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Power & Ground Name Pin 8 16 30 36 44 68 81 93 9 17 23 38 45 55 58 67 69 80 91
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
3.0 SIGNALS
Table 6. Signal Descriptions Name A15:0 Type I/O System Address Bus These address pins provide address bits 0-15 during the entire external memory cycle during both multiplexed and demultiplexed bus modes. A19:16 I/O Address Pins 16-19 These address pins provide address bits 16-19 during the entire external memory cycle during both multiplexed and demultiplexed bus modes, supporting extended addressing of the 1-Mbyte address space. NOTE: Internally, there are 24 address bits; however, only 20 external address pins (A19:0) are implemented. The internal address space is 16 Mbytes (000000-FFFFFFH) and the external address space is 1 Mbyte (00000- FFFFFH). The microcontroller resets to FF2080H in internal memory or F2080H in external memory. A19:16 share package pins with EPORT.3:0. AD15:0 I/O Address/Data Lines The function of these pins depends on the bus width and mode. 16-bit Multiplexed Bus Mode: AD15:0 drive address bits 0-15 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 8-bit Multiplexed Bus Mode: AD15:8 drive address bits 8-15 during the entire bus cycle. AD7:0 drive address bits 0-7 during the first half of the bus cycle and drive or receive data during the second half of the bus cycle. 16-bit Demultiplexed Mode: AD15:0 drive or receive data during the entire bus cycle. 8-bit Demultiplexed Mode: AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive the data that is currently on the high byte of the internal bus. ALE O Address Latch Enable This active-high output signal is asserted only during external memory cycles. ALE signals the start of an external bus cycle and indicates that valid address information is available on the system address/data bus (A19:16 and AD15:0 for a multiplexed bus; A19:0 for a demultiplexed bus). An external latch can use this signal to demultiplex address bits 0-15 from the address/data bus in multiplexed mode. Description
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8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. Signal Descriptions (Continued) Name BHE# Type O Byte High Enable
Description During 16-bit bus cycles, this active-low output signal is asserted for word and highbyte reads and writes to external memory. BHE# indicates that valid data is being transferred over the upper half of the system data bus. Use BHE#, in conjunction with address bit 0 (A0 for a demultiplexed address bus, AD0 for a multiplexed address/data bus), to determine which memory byte is being transferred over the system bus: BHE# 0 0 1
AD0 or A0 0 1 0
Byte(s) Accessed both bytes high byte only low byte only
BHE# shares a package pin with WRH#. When this pin is configured as a special-function signal (P5_MODE.5 = 1), the chip configuration register 0 (CCR0) determines whether it functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
BREQ#
O
Bus Request This active-low output signal is asserted during a hold cycle when the bus controller has a pending external memory cycle. When the bus-hold protocol is enabled (WSR.7 is set), the P2.3/BREQ# pin can function only as BREQ#, regardless of the configuration selected through the port configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is cleared). The microcontroller can assert BREQ# at the same time as or after it asserts HLDA#. Once it is asserted, BREQ# remains asserted until HOLD# is deasserted. BREQ# shares a package pin with P2.4.
CLKOUT
O
Clock Output Output of the internal clock generator. The CLKOUT frequency is 1/2 the internal operating frequency (f). CLKOUT has a 50% duty cycle. CLKOUT shares a package pin with P2.7.
CS5#:0
O
Chip-select Lines 0-5 The active-low output CSx# is asserted during an external memory cycle when the address to be accessed is in the range programmed for chip select x. If the external memory address is outside the range assigned to the six chip selects, no chipselect output is asserted and the bus configuration defaults to the CS5# values. Immediately following reset, CS0# is automatically assigned to the range FF2000- FF20FFH (F2000-F20FFH if external). CS5:0# share package pins with P3.5:0.
11
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. Signal Descriptions (Continued) Name EA# Type I External Access This input determines whether memory accesses to special-purpose and program memory partitions (FF2000-FF2FFFH) are directed to internal or external memory. These accesses are directed to internal memory if EA# is held high and to external memory if EA# is held low. For an access to any other memory location, the value of EA# is irrelevant. EA# is not latched and can be switched dynamically during normal operating mode. Be sure to thoroughly consider the issues, such as different access times for internal and external memory, before using this dynamic switching capability. Always connect EA# to VSS when using a microcontroller that has no internal nonvolatile memory. EPA3:0 I/O Event Processor Array (EPA) Capture/Compare Channels High-speed input/output signals for the EPA capture/compare channels. EPA3:0 share package pins with P1.3:0. EPORT.3:0 I/O Extended Addressing Port This is a 4-bit, bidirectional, memory-mapped port. EPORT.3:0 share package pins with A.19:16. EXTINT0 EXTINT1 EXTINT2 EXTINT3 I External Interrupts In normal operating mode, a rising edge on EXTINTx sets the EXTINTx interrupt pending bit. EXTINTx is sampled during phase 2 (CLKOUT high). The minimum high time is one state time. In standby and powerdown modes, asserting the EXTINTx signal for at least 50 ns causes the device to resume normal operation. The interrupt does not need to be enabled, but the pin must be configured as a special-function input. If the EXTINTx interrupt is enabled, the CPU executes the interrupt service routine. Otherwise, the CPU executes the instruction that immediately follows the command that invoked the power-saving mode. In idle mode, asserting any enabled interrupt causes the device to resume normal operation. EXTINT0 shares a package pin with P2.2, EXTINT1 shares a package pin with P2.4, EXTINT2 shares a package pin with P3.6, and EXTINT3 shares a package pin with P3.7. HLDA# O Bus Hold Acknowledge This active-low output indicates that the CPU has released the bus as the result of an external device asserting HOLD#. When the bus-hold protocol is enabled (WSR.7 is set), the P2.6/HLDA# pin can function only as HLDA#, regardless of the configuration selected through the port configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is cleared). Description
12
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. Signal Descriptions (Continued) Name HOLD# Type I Bus Hold Request An external device uses this active-low input signal to request control of the bus. When the bus-hold protocol is enabled (WSR.7 is set), the P2.5/HOLD# pin can function only as HOLD#, regardless of the configuration selected through the port configuration registers (P2_MODE, P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until the bus-hold protocol is disabled (WSR.7 is cleared). HOLD# shares a package pin with P2.5. INST O Instruction Fetch When high, INST indicates that an instruction is being fetched from external memory. The signal remains high during the entire bus cycle of an external instruction fetch. INST is low for data accesses, including interrupt vector fetches and chip configuration byte reads. INST is low during internal memory fetches. NMI I Nonmaskable Interrupt In normal operating mode, a rising edge on NMI generates a nonmaskable interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for greater than one state time to guarantee that it is recognized. ONCE I On-circuit Emulation Holding ONCE high during the rising edge of RESET# places the device into oncircuit emulation (ONCE) mode. This mode puts all pins into a high-impedance state, thereby isolating the device from other components in the system. The value of ONCE is latched when the RESET# pin goes inactive. While the device is in ONCE mode, you can debug the system using a clip-on emulator. To exit ONCE mode, reset the device by pulling the RESET# signal low. To prevent inadvertent entry into ONCE mode, connect the ONCE pin to VSS. P1.7:0 I/O Port 1 This is a standard, 8-bit, bidirectional port that shares package pins with individually selectable special-function signals. Port 1 shares package pins with the following signals: P1.0/EPA0, P1.1/EPA1, P1.2/EPA2, P1.3/EPA3, P1.4/T1CLK, P1.5/T1DIR, P1.6/T2CLK, and P1.7/T2DIR. P2.7:0 I/O Port 2 This is a standard, 8-bit, bidirectional port that shares package pins with individually selectable special-function signals. Port 2 shares package pins with the following signals: P2.0/TXD, P2.1/RXD, P2.2/EXTINT0, P2.3/BREQ#, P2.4/EXTINT1, P2.5/HOLD#, P2.6/HLDA#, and P2.7/CLKOUT. P3.7:0 I/O Port 3 This is a standard, 8-bit, bidirectional port that shares package pins with individually selectable special-function signals. Port 3 shares package pins with the following signals: P3.0/CS0#, P3.1/CS1#, P3.2/CS2#, P3.3/CS3#, P3.4/CS4#, P3.5/CS5#, P3.6/EXTINT2, and P3.7/EXTINT3. Description
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8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. Signal Descriptions (Continued) Name P4.3:0 Type I/O Port 4 This ia a 4-bit bidirectional, standard I/O port with high-current drive capability. Port 4 shares package pins with the following signals: P4.0/PWM0, P4.1/PWM1, and P4.2/PWM2. P4.3 has a dedicated package pin. PWM2:0 O Pulse Width Modulator Outputs These are PWM output pins with high-current drive capability. PWM2:0 share package pins with P4.2:0. RD# O Read Read-signal output to external memory. RD# is asserted only during external memory reads. RD# shares a package pin with OE#. (While most signals that share package pins are connected to the pin by programming their associated control registers, both of these signals are always connected to the pin.) READY I Ready Input This active-high input can be used to insert wait states in addition to those programmed in the chip configuration byte 0 (CCB0) and the bus control x register (BUSCONx). CCB0 is programmed with the minimum number of wait states (0-3) for an external fetch of CCB1, and BUSCONx is programmed with the minimum number of wait states (0-3) for all external accesses to the address range assigned to the chip-select x channel. If READY is low when the programmed number of wait states is reached, additional wait states are added until READY is pulled high. READY shares a package pin with P5.6. RESET# I/O Reset A level-sensitive reset input to and open-drain system reset output from the microcontroller. Either a falling edge on RESET# or an internal reset turns on a pulldown transistor connected to the RESET# pin for 16 state times. In the powerdown, standby, and idle modes, asserting RESET# causes the chip to reset and return to normal operating mode. After a device reset, the first instruction fetch is from FF2080H (or F2080H in external memory). For the 80L196NP, the program and special-purpose memory locations (FF2000-FF2FFFH) reside in external memory. For the 83L196NP, these locations can reside either in external memory or in internal ROM. RPD I Return from Powerdown Timing pin for the return-from-powerdown circuit. If your application uses powerdown mode, connect a capacitor between RPD and VSS if the internal oscillator is the clock source. The capacitor causes a delay that enables the oscillator and PLL circuitry to stabilize before the internal CPU and peripheral clocks are enabled. The capacitor is not required if your application uses powerdown mode and if an external clock input is the clock source. If your application does not use powerdown mode, leave this pin unconnected. Description
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8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. Signal Descriptions (Continued) Name RXD Type I/O Receive Serial Data In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it functions as either an input or an open-drain output for data. RXD shares a package pin with P2.1. T1CLK I Timer 1 External Clock External clock for timer 1. Timer 1 increments (or decrements) on both rising and falling edges of T1CLK. Also used in conjunction with T1DIR for quadrature counting mode. and External clock for the serial I/O baud-rate generator input (program selectable). T1CLK shares a package pin with P1.4. T2CLK I Timer 2 External Clock External clock for timer 2. Timer 2 increments (or decrements) on both rising and falling edges of T2CLK. It is also used in conjunction with T2DIR for quadrature counting mode. T2CLK shares a package pin with P1.6. T1DIR I Timer 1 External Direction External direction (up/down) for timer 1. Timer 1 increments when T1DIR is high and decrements when it is low. Also used in conjunction with T1CLK for quadrature counting mode. T1DIR shares a package pin with P1.5. T2DIR I Timer 2 External Direction External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high and decrements when it is low. It is also used in conjunction with T2CLK for quadrature counting mode. T2DIR shares a package pin with P1.7. TXD O Transmit Serial Data In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it is the serial clock output. TXD shares a package pin with P2.0. VCC VSS PWR GND Digital Supply Voltage Connect each VCC pin to the digital supply voltage. Digital Circuit Ground These pins supply ground for the digital circuitry. Connect each VSS pin to ground through the lowest possible impedance path. WR# O Write This active-low output indicates that an external write is occurring. This signal is asserted only during external memory writes. WR# shares a package pin with WRL#.
Description
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the chip configuration register 0 (CCR0) determines whether it functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. 15
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 6. Signal Descriptions (Continued) Name WRH# Type O Write High
Description During 16-bit bus cycles, this active-low output signal is asserted for high-byte writes and word writes to external memory. During 8-bit bus cycles, WRH# is asserted for all write operations. WRH# shares a package pin with BHE#.
When this pin is configured as a special-function signal (P5_MODE.5 = 1), the chip configuration register 0 (CCR0) determines whether it functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
WRL#
O
Write Low During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes and word writes to external memory. During 8-bit bus cycles, WRL# is asserted for all write operations. WRL# shares a package pin with WR#.
When this pin is configured as a special-function signal (P5_MODE.2 = 1), the chip configuration register 0 (CCR0) determines whether it functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
XTAL1
I
Input Crystal/Resonator or External Clock Input Input to the on-chip oscillator and the internal clock generators. The internal clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. When using an external clock source instead of the on-chip oscillator, connect the clock input to XTAL1. The external clock signal must meet the VIH specification for XTAL1.
XTAL2
O
Inverted Output for the Crystal/Resonator Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses an external clock source instead of the on-chip oscillator.
16
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
4.0 ADDRESS MAP
Table 7. 8XL196NP Address Map Address (Note 1) FF FFFFH FF 3000H FF 2FFFH FF 2000H FF 1FFFH FF 0100H FF 00FFH FF 0000H FE FFFFH 0F 0000H 0E FFFFH 01 0000H 00 FFFFH 00 3000H 00 2FFFH 00 2000H 00 1FFFH 00 1FE0H 00 1FDFH 00 1F00H 00 1EFFH 00 0400H 00 03FFH 00 0100H 00 00FFH 00 0018H 00 0017H 00 0000H Description External device (memory or I/O) connected to address/data bus Internal ROM or external device (memory or I/O) connected to address/data bus (determined by EA# pin) External device (memory or I/O) connected to address/data bus Reserved for ICE Overlaid memory (reserved for future devices); locations xF0000-xF00FFH are reserved for ICE 896 Kbytes of external device (memory or I/O) connected to address/data bus External device (memory or I/O) connected to address/data bus External device (memory or I/O) connected to address/data bus or remapped internal ROM Memory-mapped peripheral special-function registers (SFRs) Internal peripheral special-function registers (SFRs) External device (memory or I/O) (reserved for future devices) Upper register file (general-purpose register RAM) Lower register file (general-purpose register RAM and stack pointer) Lower register file (CPU SFRs) Notes 2 2, 3 2 4 2 2 2 2, 5, 6 2, 4, 7 4, 7, 9 6 8, 9 8, 10 4, 7, 8, 10
NOTES: 1. Internally, there are 24 address bits (A23:0); however, only 20 address lines (A19:0) are bonded out. The external address space is 1 Mbyte (00000-FFFFFH). 2. Address with indirect, indexed, or extended modes. 3. The 8XL196NP resets to internal address FF2080H (FF2080H in internal ROM or F2080H in external memory). 4. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits. 5. These areas are mapped into internal ROM if the REMAP bit (CCB1.2) is set and EA# is at logic 1. Otherwise, they are mapped to external memory. 6. WARNING: The contents or functions of these memory locations may change with future device revisions, in which case a program that relies on one or more of these locations may not function properly. 7. Refer to the 8XC196NP, 80C196NU Microcontroller User's Manual. 8. Code executed in locations 000000H to 0003FFH will be forced external. 9. Address with indirect, indexed, or extended modes or through register windows. 10. Address with direct, indirect, indexed, or extended modes.
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8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
5.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature ................................. -60C to +150C Supply Voltage with Respect to VSS ............. -0.5 V to +7.0 V Power Dissipation ........................................................ 1.5 W
OPERATING CONDITIONS*
TA (Ambient Temperature Under Bias) ..............0C to +70C VCC (Digital Supply Voltage) ............................ 2.7 V to 3.3 V FXTAL1 (Input Frequency for VCC = 2.7-3.3 V) (Note 1).............. 8 MHz to 14 MHz
NOTICE: This document contains information on products in the design phase of development. The specifications are subject to change without notice. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
NOTES:
1. This device is static and should operate below 1 Hz, but has been tested only down to 8 MHz.
5.1 DC Characteristics
Table 8. DC Characteristics at VCC = 2.7 - 3.3 V Symbol ICC Parameter VCC Supply Current Min Typ(1) 28 Max 40 Units mA Test Conditions XTAL1 = 14MHz VCC = 3.3V Device in Reset XTAL1 = 14MHz VCC = 3.3 V VCC = 3.3V VSS < VIN < VCC
IIDLE IPD ILI VIL VIH VIL1 VIH1
Idle Mode Current Powerdown Mode Current (Note 2) Input Leakage Current (all input pins except RESET) Input Low Voltage (all pins) Input High Voltage Input Low Voltage XTAL1 Input High Voltage XTAL1 -0.5 0.2 VCC +1.3 -0.5 0.7 VCC
14 50
25 75 10 0.4 VCC + 0.5 0.3 VCC VCC + 0.5
mA A A V V V V
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and with VCC = 3.0 V. 2. For temperatures below 100C, typical is 10 A. 3. For all pins except P4.3:0, which have higher drive capability. 4. If VOL is held above 0.45 V or VOH is held below Vcc-0.7 V, current on pins must be externally limited to the following values: IOL and IOH maximum on all output pins is 12 mA. 5. For all pins that were weakly pulled high during RESET. This excludes ALE, INST, and NMI, which were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3). 6. Pin capacitance is not tested. CS is based on design simulations.
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8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 8. DC Characteristics at VCC = 2.7 - 3.3 V(Continued) Symbol VOL Parameter Output Low Voltage (output configured as complementary) (Note 3,4) Output High Voltage (output configured as complementary) (Note 4) Output High Voltage on XTAL2 Output Low Voltage on P4.x (output configured as complementary) Output Low Voltage in RESET on ALE, INST, and NMI Output High Voltage in RESET (Note 5) Output Low Voltage in RESET for ONCE pin Output Low Voltage on XTAL2 Hysteresis voltage width on RESET# pin Pin Capacitance (any pin to VSS) (Note 6) RESET Pull-up Resistor 9 0.3 10 95 VCC - 0.7 0.8 0.3 0.45 VCC - 0.3 VCC - 0.7 VCC - 0.3 VCC - 0.7 0.45 0.6 0.45 Min Typ(1) Max 0.3 0.45 Units V V V V V V V V V Test Conditions IOL = 200 A IOL = 3.2 mA IOH = -200 A IOH = -3.2 mA IOH = -100 A IOH = -500 A IOL = 8 mA IOL = 10 mA IOL = 2 A
VOH
VOH2 VOL1
VOL2
VOH1 VOL3 VOL4 VTH+ -VTH- CS RRST
V V V V V pF k
IOH = -2 A IOL = 30 A IOL = 100 A IOL = 500 A
VCC = 3.3V, VIN = 2.0V
NOTES: 1. Typical values are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and with VCC = 3.0 V. 2. For temperatures below 100C, typical is 10 A. 3. For all pins except P4.3:0, which have higher drive capability. 4. If VOL is held above 0.45 V or VOH is held below Vcc-0.7 V, current on pins must be externally limited to the following values: IOL and IOH maximum on all output pins is 12 mA. 5. For all pins that were weakly pulled high during RESET. This excludes ALE, INST, and NMI, which were weakly pulled low (see VOL2) and ONCE, which was pulled medium low (see VOL3). 6. Pin capacitance is not tested. CS is based on design simulations.
19
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
35 30
ICC, IIDLE (mA)
IIDLE@VCC = 3.0 V ICC@VCC = 3.0 V
25 20 15 10 5 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz)
A4319-01
Figure 5. ICC, IIDLE versus Frequency
20
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
5.2 AC Characteristics -- Multiplexed Bus Mode
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 9. AC Characteristics, Multiplexed Bus Mode Symbol Parameter VCC = 2.7 V - 3.3 V Min Max Units
The 8XL196NP Will Meet These Specifications FXTAL1 TXTAL1 TXHCH TCLCL TCHCL TAVRL TAVWL TWHSH TRHSH TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH Input frequency on XTAL1 Period, 1/FXTAL1 XTAL1 High to CLKOUT High/Low CLKOUT Cycle Time CLKOUT High Period A15:0, CSx# Valid to RD# Low A15:0, CSx# Valid to WR# Low A19:16, CSx# Hold after WR# Rising Edge A19:16, CSx# Hold after RD# Rising Edge CLKOUT Low to ALE High ALE Low to CLKOUT High ALE Cycle Time ALE High Period AD15:0 Valid to ALE Low AD15:0 Hold after ALE Low ALE Low to RD# Low RD# Low to CLKOUT Low RD# Low Period RD# High to ALE High RD# Low to Address Float ALE Low to WR# Low CLKOUT Low to WR# Low Data Valid before WR# High CLKOUT High to WR# High WR# Low Period TXTAL1 - 30 -18 TXTAL1 - 23 -10 TXTAL1 - 10 10 10 8 71 20 2TXTAL1 TXTAL1 - 10 2TXTAL1 - 30 2TXTAL1 - 15 0 0 -12 -10 4TXTAL1 TXTAL1 - 15 TXTAL1 - 18 TXTAL1 - 25 TXTAL1 - 30 5 TXTAL1 - 10 TXTAL1 - 5 TXTAL1 + 20 5 30 TXTAL1 + 5 10 15 ns ns ns (1) ns ns ns ns ns ns (1) ns (2) ns ns ns ns (1) ns ns (1) TXTAL1 + 15 14 125 110 MHz ns ns ns ns ns ns
NOTES: 1. If wait states are used, add 2TXTAL1 x n, where n = number of wait states. 2. Assuming back-to-back bus cycles. 3. 8-bit bus only.
21
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 9. AC Characteristics, Multiplexed Bus Mode (Continued) Symbol Parameter VCC = 2.7 V - 3.3 V Min Max Units
The 8XL196NP Will Meet These Specifications TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX Data Hold after WR# High WR# High to ALE High BHE#, INST Hold after WR# High A15:8 Hold after WR# High BHE#, INST Hold after RD# High A15:8 Hold after RD# High TXTAL1 - 33 TXTAL1 - 12 TXTAL1 - 10 TXTAL1 - 30 TXTAL1 - 10 TXTAL1 - 25 TXTAL1 + 20 ns ns (2) ns ns (3) ns ns (3)
NOTES: 1. If wait states are used, add 2TXTAL1 x n, where n = number of wait states. 2. Assuming back-to-back bus cycles. 3. 8-bit bus only.
22
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 10. AC Characteristics, Multiplexed Bus Mode Symbol Parameter VCC = 2.7 V - 3.3 V Min Max Units
The External Memory System Must Meet These Specifications TAVYV TYLYH TCLYX TAVDV TRLDV TSLDV TCLDV TRHDZ TRXDX AD15:0 Valid to READY Setup Non READY Time READY Hold after CLKOUT Low AD15:0 Valid to Input Data Valid RD# Active to Input Data Valid Chip-select Low, A19:16 Valid to Data Valid CLKOUT Low to Input Data Valid End of RD# to Input Data Float Data Hold after RD# Inactive 0 2TXTAL1 - 60 No Upper Limit 0 TXTAL1 - 20 3TXTAL1 - 55 TXTAL1 - 25 4TXTAL1 - 75 TXTAL1 - 50 TXTAL1 - 10 ns ns ns ns ns ns (1) ns (2) ns (2)
NOTES: 1. Exceeding the maximum specification causes additional wait states. 2. If wait states are used, add 2TXTAL1 x n, where n = number of wait states.
Table 11. AC Timing Symbol Definitions Signals A B C D G
Conditions S W X Y BR CSx# WR#, WRH#, WRL# XTAL1 READY BREQ# H L V X Z High Low Valid No Longer Valid Floating
Address BHE# CLKOUT Data Buswidth
H HA L Q R
HOLD# HLDA# ALE Data Out RD#
Address bus (demultiplexed mode) or Address/data bus (multiplexed mode)
23
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
TXTAL1
XTAL1
TCLCL TXHCH TCHCL
CLKOUT
TRLCL TCLLH TLLCH TLHLH
ALE
TLHLL TLLRL TRLRH TRHLH
RD#
TAVLL TLLAX TRLAZ TRLDV TRHDZ
AD15:0 (read)
Address Out TAVDV TLLWL TWLWH
Data
TWHLH
WR#
TQVWH TWHQX
AD15:0 (write)
Address Out
Data Out TRHBX TWHBX
Address Out
BHE#, INST
Valid TRHAX TWHAX
AD15:8
TSLDV
Address Out
A19:16 CSx#
Address Out TWHSH TRHSH
A2844-01
Figure 6. System Bus Timing Diagram (Multiplexed Bus Mode)
24
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
TCLYX (max)
CLKOUT
TAVYV TCLYX (min)
READY
TLHLH + 2TXTAL1
ALE
TRLRH + 2TXTAL1
RD# AD15:0 (read) WR#
TRLDV + 2TXTAL1 TAVDV + 2TXTAL1 Address Out TWLWH + 2TXTAL1 Data In
TQVWH + 2TXTAL1
AD15:0 (write) BHE#, INST A19:16 CSx#
Address Out
Data Out
Extended Address Out
A3250-01
Figure 7. READY Timing Diagram (Multiplexed Bus Mode)
25
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
5.3 AC Characteristics -- Demultiplexed Bus Mode
Test Coditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns.
Table 12. AC Characteristics, Demultiplexed Bus Mode Symbol Parameter VCC = 2.7 V - 3.3 V Min Max Units
The 8XL196NP Will Meet These Specifications FXTAL1 TXTAL1 TXHCH TCLCL TCHCL TAVRL TAVWL TCLLH TLLCH TLHLH TLHLL TRLCH TRLRH TRHLH TWLCH TQVWH TCHWH TWLWH TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX Input requency on XTAL1 Period, 1/FXTAL1 XTAL1 High to CLKOUT High/Low CLKOUT Cycle Time CLKOUT High Period A19:0, CSx# Valid to RD# Low A19:0, CSx# Valid to WR# Low CLKOUT Low to ALE High ALE Low to CLKOUT High ALE Cycle Time ALE High Period RD# Low to CLKOUT High RD# Low Period RD# High to ALE High WR# Low to CLKOUT High Data Valid before WR# High CLKOUT High to WR# High WR# Low Period Data Hold after WR# High WR# High to ALE High BHE#, INST Hold after WR# High A19:0, CSx# Hold after WR# High BHE#, INST Hold after RD# High A19:0, CSx# Hold after RD# High 8 71 20 2TXTAL1 TXTAL1 - 10 2TXTAL1 - 48 2TXTAL1 - 37 - 12 - 15 4TXTAL1 TXTAL1 - 12 -5 2TXTAL1 - 10 TXTAL1 - 5 - 10 3TXTAL1 - 55 - 15 2TXTAL1 - 13 TXTAL1 - 25 TXTAL1 - 10 TXTAL1 - 10 0 TXTAL1 - 10 0 TXTAL1 + 20 5 TXTAL1 + 20 10 TXTAL1 + 10 20 10 15 TXTAL1 + 15 14 125 110 MHz ns ns ns ns ns ns ns ns ns (1) ns ns ns (1) ns (2) ns ns (1) ns ns (1) ns ns (2) ns ns ns ns
NOTES: 1. If wait states are used, add 2TXTAL1 x n, where n = number of wait states. 2. Assuming back-to-back bus cycles.
26
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
Table 13. AC Characteristics, Demultiplexed Bus Mode Symbol Parameter VCC = 2.7 V - 3.3 V Min Max Units
The External Memory System Must Meet These Specifications TAVYV TYLYH TCLYX TAVDV TRLDV TCLDV TRHDZ TRXDX A19:0, CSx# Valid to READY Setup Non READY Time READY Hold after CLKOUT Low A19:0, CSx# Valid to Input Data Valid RD# Active to Input Data Valid CLKOUT Low to Input Data Valid End of RD# to Input Data Float Data Hold after RD# Inactive 0 3TXTAL1 - 88 No Upper Limit TXTAL1 - 30 4TXTAL1 - 75 2TXTAL1 - 33 TXTAL1 - 50 TXTAL1 - 5 ns ns ns (1) ns (2) ns (2) ns ns ns
NOTES: 1. Exceeding the maximum specification causes additional wait states. 2. If wait states are used, add 2TXTAL1 x n, where n = number of wait states.
27
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
TXTAL1
XTAL1
TCLCL TXHCH TCHCL
CLKOUT
TCLDV TLHLH
TCLLH
TLLCH
ALE
TLHLL TRLCH TRLRH TRHLH
RD#
TRLDV TRHDZ
AD15:0 (read)
TAVDV TWLWH TWLCH TQVWH
Valid TCHWH TWHLH
WR#
TWHQX
AD15:0 (write)
Valid TRHBX TWHBX
BHE#, INST
Valid
TRHAX
TWHAX Address
A19:0 CSx#
Address Out
A2845-01
Figure 8. System Bus Timing Diagram (Demultiplexed Bus Mode)
28
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
TCLYX (max)
CLKOUT
TAVYV TCLYX (min)
READY
TLHLH + 2TXTAL1
ALE
TRLRH + 2TXTAL1
RD#
TRLDV + 2TXTAL1 TAVDV + 2TXTAL1
AD15:0 (read)
TWLWH + 2TXTAL1
Data
WR#
TQVWH + 2TXTAL1
AD15:0 (write) BHE#, INST A19:0 CSx#
Data Out
Extended Address Out
A3256-01
Figure 9. READY Timing Diagram (Demultiplexed Bus Mode)
29
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
5.4 HOLD#/HLDA# Timing
Table 14. HOLD#/HLDA# Timings Symbol THVCH TCLHAL TCLBRL THALAZ THALBZ TCLHAH TCLBRH THAHAX THAHBV Parameter HOLD# Setup Time (to guarantee recognition at next clock) CLKOUT Low to HLDA# Low CLKOUT Low to BREQ# Low HLDA# Low to Address Float HLDA# Low to BHE#, INST, RD#, WR# Weakly Driven CLKOUT Low to HLDA# High CLKOUT Low to BREQ# High HLDA# High to Address No Longer Floating HLDA# High to BHE#, INST, RD#, WR# Valid -25 -25 -20 -20 VCC = 2.7 V - 3.3V Min 83 -15 -15 15 15 33 25 15 25 Max Units ns ns ns ns ns ns ns ns ns
CLKOUT
THVCH
HOLD#
THVCH
Hold Latency
TCLHAL
HLDA#
TCLHAH
TCLBRL
BREQ#
TCLBRH
THALAZ
A19:0, AD15:0 CSx#, BHE#, INST, RD#, WR# WRL#, WRH# ALE
THAHAX THAHBV
Weakly held inactive
THALBZ
TCLLH
Start of strongly driven ALE
A2460-03
Figure 10. HOLD#/HLDA# Timing Diagram
30
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
5.5 AC Characteristics -- Serial Port, Shift Register Mode
Table 15. Serial Port Timing -- Shift Register Mode Symbol TXLXL Parameter Serial Port Clock period (BRR x002H) (BRR = x001H) (Note 1) Output data setup to clock high Output data hold after clock high Next output data valid after clock high Input data setup to clock high Input data hold after clock high Last clock high to output float 2TXTAL1 + 50 0 5TXTAL1+ 30 VCC = 2.7 V - 3.3V Min 6TXTAL1 4TXTAL1 3TXTAL1 - 30 2TXTAL1 - 90 2TXTAL1 + 50 Max Units
ns ns ns ns ns ns ns ns
TQVXH TXHQX TXHQV TDVXH TXHDX TXHQZ
NOTE: 1. The minimum baud-rate register value for receptions is x002H and the minimum baud-rate register value for transmissions is x001H.
TXLXL TXD TQVXH RXD (Out) 0 TDVXH RXD (In) Valid Valid Valid 1 2 3 TXHDX Valid Valid Valid Valid Valid 4
TXLXH
TXHQV TXHQX 5 6 TXHQZ 7
A2080-02
Figure 11. Serial Port Waveform -- Shift Register Mode
31
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
5.6 External Clock Drive
Table 16. External Clock Drive Symbol 1/TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Input frequency Period (TXTAL1) High Time Low Time Rise Time Fall Time Min 8 71 0.35TXTAL1 0.35TXTAL1 Max 14 125 0.65TXTAL1 0.65TXTAL1 10 10 Units MHz ns ns ns ns ns
TXHXX 0.7 VCC + 0.5 V
TXLXH 0.7 VCC + 0.5 V
XLXX
TXHXL
T
0.3 VCC - 0.5 V T
0.3 VCC - 0.5 V
XLXL
A2119-02
Figure 12. External Clock Drive Waveforms
5.7 Test Output Waveforms
2.5 V
1.6 V
1.6 V
Test Points
0.25 V 0.5 V 0.5 V
AC testing inputs are driven at 2.5 V for a logic "1" and 0.25 V for a logic "0". Timing measurements are made at 1.6 V for a logic "1" and 0.5 V for a logic "0".
A2740-01
Figure 13. AC Testing Output Waveforms During 3.0 Volt Testing
32
8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
VLOAD + 0.15 V VLOAD VLOAD - 0.15 V Timing Reference Points
VOH - 0.15 V
VOL + 0.15 V
For timing purposes, a port pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL level occurs with IOL/IOH 10 mA.
A2739-01
Figure 14. Float Waveforms During 3.0 Volt Testing
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8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.0 THERMAL CHARACTERISTICS
All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values will change depending on operating conditions and the application. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. Table 17. Thermal Characteristics Package Type 100-pin SQFP 100-pin QFP JA 55C/W 56C/W JC 14C/W 16C/W
7.0 8XL196NP ERRATA
Change identifiers have been used on embedded products since 1990. The change identifier is the last character in the FPO number. The FPO number is typically a nine character number located on the second line of the topside package mark. The following errata listing is applicable to the B-step (denoted by a "B" or "C" at the end of the topside tracking number): 1. Any jump, conditional jump, or call instruction located within six bytes of the top of a page, i.e., 0FFFA-0FFFFH, may cause a jump to the wrong page. To ensure this problem does not occur, place at least six NOPs at the top of each page.
8.0 DATASHEET REVISION HISTORY
This datasheet is valid for devices with an "A" at the end of the topside tracking number. Datasheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices.
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